Misclock

When misclock occurs, it is recorded as an audio datum and an alarm is given.

After each phase crossing there is a chance of a misclock being produced by jitter induced phase reversal at subsequent clocking edges.

We will present a model to determine this minimum difference frequency given the acceptable risk of a misclock.

This glitch can misclock the DMA state controller and indirectly mess up the memory unit in use.

We didn't get past the start. It was misclocked opened and we got too much lox flow in the main chamber early.

This occurred despite an alignment pin design feature to prevent misclocking. It occurred despite a sensitivity test of the system a few days before liftoff to confirm live activity and correct polarity of all of the rate gyros.

How else could they misclock one of the disappearance intervals by more than a month?